A layout of logic circuits is performed in order to manufacture a semiconductor device having logic circuits. A cell is manufactured for each function, which is used as a basic cell (also referred to as a standard cell or the like), and a plurality of the basic cells are electrically connected to each other through wirings to perform the layout of the logic circuits. The placement of the plurality of basic cells and connection through wirings are performed using an automatic placement and routing tool. Note that a wiring is referred to as a routing in this specification.
For example, FIG. 2 shows a design flow in the case where the layout of the logic circuits is performed using an automatic placement and routing tool. The layout of the logic circuits is performed through steps of functional design, logic synthesis, automatic placement and routing, and the like.
In the functional design, operation of a functional circuit is described by a hardware description language (hereinafter HDL). Simulation is performed as appropriate to confirm such as whether the function of an objective functional circuit is realized.
In the logic synthesis, operation described by the above HDL is rewritten into an actual electric circuit using a logic synthesis tool. This electric circuit can be obtained through a mechanism which is generally referred to as a netlist. The netlist is connection information of an input terminal or an output terminal of a basic cell included in the electric circuit. At the time of the logic synthesis, first, temporary parasitic capacitance in each wiring is decided, a basic cell having driving capability in accordance with the parasitic capacitance is selected by the logic synthesis tool, and the netlist is optimized so as to satisfy a predetermined specification such as operation speed.
In the automatic placement and routing, a photomask is made based on the netlist. First, temporary placement of the basic cells included in the netlist is performed, and an input terminal and an output terminal of each basic cell are electrically connected to each other in sequence in accordance with the netlist. The photomask is completed by electrically connecting all terminals.
After the automatic placement and routing is performed, parasitic capacitance in each wiring is extracted, and the operation speed is estimated again. In the case where the predetermined specification is not satisfied at the time of verifying this operation, the phase returns to the automatic placement and routing or the logic synthesis. When the phase returns to the logic synthesis, the parasitic capacitance after the placement and routing is used instead of the value of the temporary parasitic capacitance in each wiring. These steps are repeated when a predetermined specification is not obtained sequentially. Accordingly, in the automatic placement and routing, placement of a plurality of basic cells and wiring connection are performed in consideration of operation speed and delay time of each basic cell (for example, see Reference 1).